1. Field of the Invention
This invention relates to a fabrication method of a trenched metal-oxide-semiconductor (MOS) device, and more particularly relates to a fabrication method of a trenched MOS device with low gate-to-drain charge (Qgd).
2. Description of Related Art
In contrast with typical planar metal-oxide-semiconductor (MOS) devices with current flow substantially parallel to the surface of the semiconductor base, trenched MOS devices with gate electrodes thereof allocated in the trenches for generating perpendicular current flow have the potential to reduce cell size and material cost. Among all the MOS devices in the market, metal-oxide-semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are two common MOS devices for power applications.
The energy losses in a MOS device include conduction loss due to conduction resistance and switching loss due to gate-to-drain charge (Qgd). With the increasing of operating frequency, switching loss becomes a dominant factor for the problem of energy loss. It is understood that switching loss can be reduced by lowering gate-to-drain capacitance (Cgd) of the MOS devices. However, typical fabrication methods for lowering gate-to-drain capacitance of the MOS devices are quite complicated and costly.
Accordingly, it is an important issue in the field to find out a simple method to fabricate a trenched MOS device with low gate-to-drain capacitance.